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DFI K6bv3+: maximum cacheable memory?

 
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pigdos

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Since: Dec 23, 2005
Posts: 114



(Msg. 1) Posted: Fri Jul 07, 2006 6:57 am
Post subject: DFI K6bv3+: maximum cacheable memory?
Archived from groups: alt>comp>periphs>mainboard>fic (more info?)

I have a DFI k6bv3+ w/2MB L2 cache. I'm figuring that if the VA503+ can
cache 256MB w/1MB of L2 cache the k6bv3+ can probably cache 512MB w/2MB of
L2 cache? The tag RAM size would be the determining factor here right? I'm
assuming write-through mode for the L2 cache.

--
Doug

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Alex Zorrilla

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Since: May 14, 2004
Posts: 181



(Msg. 2) Posted: Fri Jul 07, 2006 5:09 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

Yes, that is correct for the MVP3/MVP4. If you were using write-back
mode for the L2 cache, that would limit you to 1/2 the cacheable RAM, so
that would be 256 MB with 2 MB L2 cache. For write-through, a 2 MB L2
cache would give you 512 MB cacheable RAM.




pigdos wrote:
> I have a DFI k6bv3+ w/2MB L2 cache. I'm figuring that if the VA503+ can
> cache 256MB w/1MB of L2 cache the k6bv3+ can probably cache 512MB w/2MB of
> L2 cache? The tag RAM size would be the determining factor here right? I'm
> assuming write-through mode for the L2 cache.
>

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farmuse10

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Since: Feb 01, 2005
Posts: 90



(Msg. 3) Posted: Sat Jul 08, 2006 2:46 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

I was under the impression that it was more dependent on the CPU used
than any BIOS setting. The K6-2 can cache 256, where as the K 6 III line
can cache much more than that. I doubt if either board would be able to
use 512 MB modules, so 512 total would be the max with a K 6 III.



Alex Zorrilla wrote:
> Yes, that is correct for the MVP3/MVP4. If you were using write-back
> mode for the L2 cache, that would limit you to 1/2 the cacheable RAM, so
> that would be 256 MB with 2 MB L2 cache. For write-through, a 2 MB L2
> cache would give you 512 MB cacheable RAM.
>
>
>
>
> pigdos wrote:
>
>> I have a DFI k6bv3+ w/2MB L2 cache. I'm figuring that if the VA503+
>> can cache 256MB w/1MB of L2 cache the k6bv3+ can probably cache 512MB
>> w/2MB of L2 cache? The tag RAM size would be the determining factor
>> here right? I'm assuming write-through mode for the L2 cache.
>>
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pigdos

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Since: Dec 23, 2005
Posts: 114



(Msg. 4) Posted: Sun Jul 09, 2006 7:11 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

We're not talking about the on-board cache on the CPU we're talking about
the motherboard cache, which could be L2 (if you had a K6, Pentium, K62 or
Cyrix CPU) or L3 (if you had a K62+ or K63+).

--
Doug
"farmuse" wrote in message

> I was under the impression that it was more dependent on the CPU used
> than any BIOS setting. The K6-2 can cache 256, where as the K 6 III line
> can cache much more than that. I doubt if either board would be able to
> use 512 MB modules, so 512 total would be the max with a K 6 III.
>
>
>
> Alex Zorrilla wrote:
>> Yes, that is correct for the MVP3/MVP4. If you were using write-back
>> mode for the L2 cache, that would limit you to 1/2 the cacheable RAM, so
>> that would be 256 MB with 2 MB L2 cache. For write-through, a 2 MB L2
>> cache would give you 512 MB cacheable RAM.
>>
>>
>>
>>
>> pigdos wrote:
>>
>>> I have a DFI k6bv3+ w/2MB L2 cache. I'm figuring that if the VA503+ can
>>> cache 256MB w/1MB of L2 cache the k6bv3+ can probably cache 512MB w/2MB
>>> of L2 cache? The tag RAM size would be the determining factor here
>>> right? I'm assuming write-through mode for the L2 cache.
>>>
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John and Karen

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Since: Jul 16, 2006
Posts: 3



(Msg. 5) Posted: Sun Jul 16, 2006 8:22 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

it is dependent on the cpu not the size of the L2

On Sat, 08 Jul 2006 23:11:54 -0400, pigdos wrote:

> We're not talking about the on-board cache on the CPU we're talking about
> the motherboard cache, which could be L2 (if you had a K6, Pentium, K62
> or
> Cyrix CPU) or L3 (if you had a K62+ or K63+).
>



--
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Alex Zorrilla

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Since: May 14, 2004
Posts: 181



(Msg. 6) Posted: Mon Jul 17, 2006 2:58 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

In the case of the K6-2, K6, Pentium MMX, Cyrix M-II, and other similar
processors, it is quite dependent on the amount of the L2 cache on the
motherboard. These CPUs do not have their own L2 cache, so the chipsets
designed to run them (e.g., Intel 430TX, VIA MVP3, SiS 5597/5598) make
use of the tag RAM on the motherboard's L2 cache to determine the amount
of cacheable system RAM. The actual amount of cacheable RAM depends on
the chipset, the amount of tag RAM available in the L2, and certain BIOS
settings.

Now, when the L2 was moved to the CPU (Pentium Pro, Pentium II, K6-III,
Athlon), the amount of tag RAM still makes a difference, but now it
becomes a function of the CPU in question, as opposed to the motherboard.





John and Karen wrote:
> it is dependent on the cpu not the size of the L2
>
> On Sat, 08 Jul 2006 23:11:54 -0400, pigdos wrote:
>
>> We're not talking about the on-board cache on the CPU we're talking about
>> the motherboard cache, which could be L2 (if you had a K6, Pentium,
>> K62 or
>> Cyrix CPU) or L3 (if you had a K62+ or K63+).
>>
>
>
>
> --Using Opera's revolutionary e-mail client: http://www.opera.com/mail/
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John and Karen

External


Since: Jul 16, 2006
Posts: 3



(Msg. 7) Posted: Wed Jul 19, 2006 1:46 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

I know all that, but for the K6 2 vs K6 III is makes a difference.

On Mon, 17 Jul 2006 11:58:15 -0400, Alex Zorrilla wrote:

> In the case of the K6-2, K6, Pentium MMX, Cyrix M-II, and other similar
> processors, it is quite dependent on the amount of the L2 cache on the
> motherboard. These CPUs do not have their own L2 cache, so the chipsets
> designed to run them (e.g., Intel 430TX, VIA MVP3, SiS 5597/5598) make
> use of the tag RAM on the motherboard's L2 cache to determine the amount
> of cacheable system RAM. The actual amount of cacheable RAM depends on
> the chipset, the amount of tag RAM available in the L2, and certain BIOS
> settings.
>
> Now, when the L2 was moved to the CPU (Pentium Pro, Pentium II, K6-III,
> Athlon), the amount of tag RAM still makes a difference, but now it
> becomes a function of the CPU in question, as opposed to the motherboard.
>
>
>
>
>
> John and Karen wrote:
>> it is dependent on the cpu not the size of the L2
>> On Sat, 08 Jul 2006 23:11:54 -0400, pigdos wrote:
>>
>>> We're not talking about the on-board cache on the CPU we're talking
>>> about
>>> the motherboard cache, which could be L2 (if you had a K6, Pentium,
>>> K62 or
>>> Cyrix CPU) or L3 (if you had a K62+ or K63+).
>>>
>> --Using Opera's revolutionary e-mail client:
>> http://www.opera.com/mail/



--
Using Opera's revolutionary e-mail client: http://www.opera.com/mail/
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Alex Zorrilla

External


Since: May 14, 2004
Posts: 181



(Msg. 8) Posted: Wed Jul 19, 2006 2:43 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

Ahhh, OK. Now I see what you mean. Agreed.


John and Karen wrote:
> I know all that, but for the K6 2 vs K6 III is makes a difference.
>
> On Mon, 17 Jul 2006 11:58:15 -0400, Alex Zorrilla wrote:
>
>> In the case of the K6-2, K6, Pentium MMX, Cyrix M-II, and other
>> similar processors, it is quite dependent on the amount of the L2
>> cache on the motherboard. These CPUs do not have their own L2 cache,
>> so the chipsets designed to run them (e.g., Intel 430TX, VIA MVP3, SiS
>> 5597/5598) make use of the tag RAM on the motherboard's L2 cache to
>> determine the amount of cacheable system RAM. The actual amount of
>> cacheable RAM depends on the chipset, the amount of tag RAM available
>> in the L2, and certain BIOS settings.
>>
>> Now, when the L2 was moved to the CPU (Pentium Pro, Pentium II,
>> K6-III, Athlon), the amount of tag RAM still makes a difference, but
>> now it becomes a function of the CPU in question, as opposed to the
>> motherboard.
>>
>>
>>
>>
>>
>> John and Karen wrote:
>>> it is dependent on the cpu not the size of the L2
>>> On Sat, 08 Jul 2006 23:11:54 -0400, pigdos wrote:
>>>
>>>> We're not talking about the on-board cache on the CPU we're talking
>>>> about
>>>> the motherboard cache, which could be L2 (if you had a K6, Pentium,
>>>> K62 or
>>>> Cyrix CPU) or L3 (if you had a K62+ or K63+).
>>>>
>>> --Using Opera's revolutionary e-mail client:
>>> http://www.opera.com/mail/
>
>
>
> --Using Opera's revolutionary e-mail client: http://www.opera.com/mail/
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pigdos

External


Since: Dec 23, 2005
Posts: 114



(Msg. 9) Posted: Wed Jul 26, 2006 6:20 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

And you're still wrong because it STILL makes a difference in how much RAM
the motherboard cache can handle REGARDLESS of the type of CPU you have
installed.

--
Doug
"John and Karen" wrote in message

> I know all that, but for the K6 2 vs K6 III is makes a difference.
>
> On Mon, 17 Jul 2006 11:58:15 -0400, Alex Zorrilla wrote:
>
>> In the case of the K6-2, K6, Pentium MMX, Cyrix M-II, and other similar
>> processors, it is quite dependent on the amount of the L2 cache on the
>> motherboard. These CPUs do not have their own L2 cache, so the chipsets
>> designed to run them (e.g., Intel 430TX, VIA MVP3, SiS 5597/5598) make
>> use of the tag RAM on the motherboard's L2 cache to determine the amount
>> of cacheable system RAM. The actual amount of cacheable RAM depends on
>> the chipset, the amount of tag RAM available in the L2, and certain BIOS
>> settings.
>>
>> Now, when the L2 was moved to the CPU (Pentium Pro, Pentium II, K6-III,
>> Athlon), the amount of tag RAM still makes a difference, but now it
>> becomes a function of the CPU in question, as opposed to the motherboard.
>>
>>
>>
>>
>>
>> John and Karen wrote:
>>> it is dependent on the cpu not the size of the L2
>>> On Sat, 08 Jul 2006 23:11:54 -0400, pigdos wrote:
>>>
>>>> We're not talking about the on-board cache on the CPU we're talking
>>>> about
>>>> the motherboard cache, which could be L2 (if you had a K6, Pentium,
>>>> K62 or
>>>> Cyrix CPU) or L3 (if you had a K62+ or K63+).
>>>>
>>> --Using Opera's revolutionary e-mail client:
>>> http://www.opera.com/mail/
>
>
>
> --
> Using Opera's revolutionary e-mail client: http://www.opera.com/mail/
 >> Stay informed about: DFI K6bv3+: maximum cacheable memory? 
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farmuse10

External


Since: Feb 01, 2005
Posts: 90



(Msg. 10) Posted: Thu Jul 27, 2006 8:12 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

I know the FIC 503+ can cache more ram with the K6 III than it can
with the K6-2. there are many instances where this is true, where what
CPU you use makes a difference. There are some P II that can cache a lot
less than other P II that run at the same speed. Believe it or not.
Because the L2 cache is on the K6 III chip itself then it is a different
configuration than with the K6-2.

pigdos wrote:

> And you're still wrong because it STILL makes a difference in how much RAM
> the motherboard cache can handle REGARDLESS of the type of CPU you have
> installed.
>
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pigdos

External


Since: Dec 23, 2005
Posts: 114



(Msg. 11) Posted: Fri Jul 28, 2006 6:47 pm
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

You really don't know much about cache architecture do you? The cache
implemented on the FIC VA503+ or K6bv3+ is entirely independent of the CPU
used. If you have L2 cache on the CPU, the on-board motherboard cache
becomes L3. The CPU used DOESN'T make a difference at ALL in the amount of
cacheable memory w.r.t. the motherboard cache. The tag RAM (and how it's
configured [write-through or write-back]) and cache size on the motherboard
are the ONLY determining factors in how much memory is cacheable on the FIC
VA503+ or DFI K6bv3.

--
Doug
"farmuse" wrote in message

> I know the FIC 503+ can cache more ram with the K6 III than it can
> with the K6-2. there are many instances where this is true, where what CPU
> you use makes a difference. There are some P II that can cache a lot less
> than other P II that run at the same speed. Believe it or not. Because the
> L2 cache is on the K6 III chip itself then it is a different configuration
> than with the K6-2.
>
> pigdos wrote:
>
>> And you're still wrong because it STILL makes a difference in how much
>> RAM the motherboard cache can handle REGARDLESS of the type of CPU you
>> have installed.
>>
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John and Karen

External


Since: Jul 16, 2006
Posts: 3



(Msg. 12) Posted: Sun Jul 30, 2006 11:03 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

scroll down and see that the K6 III can cache 4 GB total ram. You did
not state what CPU you plan on using. You might be right, with 2 MB
external L2 cache on the motherboard the total ram that can be cached
might go up to 512 MB or maybe even 768, when using a K6-2. With the K6
III of any flavor, I know it can use all 768 when using the DFI board you
have.

http://www.sandpile.org/impl/k6.htm


On Fri, 28 Jul 2006 10:47:25 -0400, pigdos wrote:

> You really don't know much about cache architecture do you? The cache
> implemented on the FIC VA503+ or K6bv3+ is entirely independent of the
> CPU
> used. If you have L2 cache on the CPU, the on-board motherboard cache
> becomes L3. The CPU used DOESN'T make a difference at ALL in the amount
> of
> cacheable memory w.r.t. the motherboard cache. The tag RAM (and how it's
> configured [write-through or write-back]) and cache size on the
> motherboard
> are the ONLY determining factors in how much memory is cacheable on the
> FIC
> VA503+ or DFI K6bv3.
>



--
Using Opera's revolutionary e-mail client: http://www.opera.com/mail/
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pigdos

External


Since: Dec 23, 2005
Posts: 114



(Msg. 13) Posted: Mon Jul 31, 2006 5:04 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

Once again you have the right answer to the WRONG question. You really don't
have a clue do you? Are you even an A+?

--
Doug
"John and Karen" wrote in message

> scroll down and see that the K6 III can cache 4 GB total ram. You did
> not state what CPU you plan on using. You might be right, with 2 MB
> external L2 cache on the motherboard the total ram that can be cached
> might go up to 512 MB or maybe even 768, when using a K6-2. With the K6
> III of any flavor, I know it can use all 768 when using the DFI board you
> have.
>
> http://www.sandpile.org/impl/k6.htm
>
>
> On Fri, 28 Jul 2006 10:47:25 -0400, pigdos wrote:
>
>> You really don't know much about cache architecture do you? The cache
>> implemented on the FIC VA503+ or K6bv3+ is entirely independent of the
>> CPU
>> used. If you have L2 cache on the CPU, the on-board motherboard cache
>> becomes L3. The CPU used DOESN'T make a difference at ALL in the amount
>> of
>> cacheable memory w.r.t. the motherboard cache. The tag RAM (and how it's
>> configured [write-through or write-back]) and cache size on the
>> motherboard
>> are the ONLY determining factors in how much memory is cacheable on the
>> FIC
>> VA503+ or DFI K6bv3.
>>
>
>
>
> --
> Using Opera's revolutionary e-mail client: http://www.opera.com/mail/
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Kyle

External


Since: Jul 30, 2004
Posts: 66



(Msg. 14) Posted: Mon Aug 14, 2006 5:09 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

"pigdos" wrote in message

| Do you know what motherboard cache is?
| Do you realize it has nothing to do w/the CPU installed?

Much too simply stated to be absolutely accurate information.

This web page:
http://www3pub.amd.com/products/cpg/k6iii/trilevel.html
explains how the CPU onboard cache can have a major impact on system
performance, even when a traditional mobo L2 cache is present.

| I don't care if you've been installing computers for
| nine years
| or 20 years (I've been working with computers since 1987, I've
worked on the
| original IBM PC).

Using a CPU such as a k6III or a k62+/3+ CPU makes a world of
difference, particularly since the onboard cache of these CPUs runs at
full CPU speed, rather than at FSB speed, and will cache the entire
addressable memory space of the processor. The motherboard L2 cache
becomes relegated to an "L3" role with these CPUs, and becomes much
less important to overall performance due to its slower speed.

| It's obvious you don't understand the difference between
| cache built into a motherboard (which was common 10 years ago) and
that
| which resides in the CPU. I was never asking about how much RAM the
CPU can
| cache.
|

Now, if one installs more ram than the original mobo design will
cache, certain CPUs will still cache the "uncached" memory space not
cached by the mobo cache. I don't really understand all this
squabble.

It is well documented that once cache size exceeds 512k, only marginal
performance gains will be realized in overall memory performance
(typical usage), even when more sophisticated 4-way associative logic
is implemented. The tag ram limitations of the MVP3 chipset are
another issue well suited for a separate google search (a little
usenet searching will reveal all of the great posts on this subject,
particularly how the mvp3 chipset designs typically do not cache all
of 256 meg of memory in write-thru mode due to the 10 bit tag-ram
implementation).

--
Best regards,
Kyle
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pigdos

External


Since: Dec 23, 2005
Posts: 114



(Msg. 15) Posted: Fri Sep 22, 2006 12:43 am
Post subject: Re: DFI K6bv3+: maximum cacheable memory? [Login to view extended thread Info.]
Archived from groups: per prev. post (more info?)

This post has nothing to do w/performance whatsoever. Did you read the topic
subject? Reading comprehension counts.

The address space cached by the on-board motherboard cache has NOTHING to do
w/the CPU. Absolutely nothing. I don't care WHICH socket 7 CPU you install,
it will NOT affect the address space cached by the on-board motherboard
cache. I'm willing to bet $100.00 that regardless of which CPU is installed
Ray Van Tassle's Cachechk will still indicate the same address space as
being cached by the same motherboard cache (regardless of whether or not it
is L2 or L3) in the same mode (i.e. writethrough or writeback).

Obviously, the glue logic between the on-board motherboard cache and the CPU
has to be there, so yes, obviously it has something to do w/the CPU
installed, but only in the sense that the CPU must conform to the socket 7
specifications.

I originally asked the above question (see the post subject) and this a$$hat
began spouting off how much memory a CPU could cache.

--
Doug
"Kyle" wrote in message

> "pigdos" wrote in message
>
> | Do you know what motherboard cache is?
> | Do you realize it has nothing to do w/the CPU installed?
>
> Much too simply stated to be absolutely accurate information.
>
> This web page:
> http://www3pub.amd.com/products/cpg/k6iii/trilevel.html
> explains how the CPU onboard cache can have a major impact on system
> performance, even when a traditional mobo L2 cache is present.
>
> | I don't care if you've been installing computers for
> | nine years
> | or 20 years (I've been working with computers since 1987, I've
> worked on the
> | original IBM PC).
>
> Using a CPU such as a k6III or a k62+/3+ CPU makes a world of
> difference, particularly since the onboard cache of these CPUs runs at
> full CPU speed, rather than at FSB speed, and will cache the entire
> addressable memory space of the processor. The motherboard L2 cache
> becomes relegated to an "L3" role with these CPUs, and becomes much
> less important to overall performance due to its slower speed.
>
> | It's obvious you don't understand the difference between
> | cache built into a motherboard (which was common 10 years ago) and
> that
> | which resides in the CPU. I was never asking about how much RAM the
> CPU can
> | cache.
> |
>
> Now, if one installs more ram than the original mobo design will
> cache, certain CPUs will still cache the "uncached" memory space not
> cached by the mobo cache. I don't really understand all this
> squabble.
>
> It is well documented that once cache size exceeds 512k, only marginal
> performance gains will be realized in overall memory performance
> (typical usage), even when more sophisticated 4-way associative logic
> is implemented. The tag ram limitations of the MVP3 chipset are
> another issue well suited for a separate google search (a little
> usenet searching will reveal all of the great posts on this subject,
> particularly how the mvp3 chipset designs typically do not cache all
> of 256 meg of memory in write-thru mode due to the 10 bit tag-ram
> implementation).
>
> --
> Best regards,
> Kyle
>
>
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